10:38 AM
Write a program in verilog to implement half adder/full adder/subtractor


1. Open a new project from the drop down menu by clicking in FILE given on the
top left of the screen.
2. Create a new project and name it.
3. Click on next to enter the device properties.
4. Select the appropriate properties according to the hardware to be used.
5. Click on the next button to enter the new source.
6. Here select the Verilog MODULE and give the file name.
7. Click on next button and enter the entity name.
8. Select the define module.
9. Select the ports as input and output and name them.
10. Click on next and then to on finish.
11. Write the code for the project under the library entity.
12. Save the program.
13. Select the behavioral simulation option from the three modeling options.
14. Now select the syntax check.
15. If the syntax check comes out to be correct, then precede further, otherwise check
16. Now select simulation option and select the test bench option.
17. Initialize the clock and other properties from the window that appears on the
18. Give the clock pulse to one of the inputs and save the program.
19. Click on simulate to get the output.

Half Adder Using Assign Statement

module halfadder (Cout, sum,a,b)
input a,b;
output Cout, sum);
assign sum = a ^ b;
assign Cout = a & b;
Half Adder Gate level Description
module halfadder (Cout, sum,a,b)
input a,b;
output Cout, sum;
xor (sum, a, b);
and (Cout ,a,b);


Module half_addertb();
Reg a,b;
Wire Cout,sum;
Half_adder A1(a,b,Cout,sum);
Begin a=0;b=0;
#2 a=0;b=1;
#2 a=1;b=0;
#2 a=1;b=1;
#2 $stop;

Full Adder Using Assign statement

module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co;
assign s = a ^ b ^ ci;
assign co = (a & b) | (a & ci) | (b & ci);

Full Adder with Gate level Description

module full_adder (a, b, ci, s, co);
input a, b, ci;
output s, co);
wire NET1, NET2, NET3, NET4 ;
xor ( NET1, a, b ); xor ( s , NET1, ci );
and ( NET2, a, b );
and ( NET3, a, ci );
and ( NET4, b, ci );
or ( co, NET2, NET3, NET4 );


Module full_addertb();
reg a,b,ci;
Wire co,s;
full_adder A1(a,b,ci,s,co);
Initial Begin a=0;b=0;c=0
#2 a=0;b=0;c=1
#2 a=0;b=1;c=1
#2 a=1;b=0;c=1
#2 a=1;b=1;c=1
#2 $stop;

Half Substractor Gate level Description

module halfsubtractor (difference, borrow,a,b);
output difference, borrow;
input a,b;
wire Abar;
not #1 n1 (Abar, a);
and #1 a1(borrow,Abar,b);
xor #2 x1 (difference,a,b);

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