10:33 AM
Write a program in verilog to implement multiplexer and demultiplexer
1. Open a new project from the drop down menu by clicking in FILE given on the top
left of the screen.
2. Create a new project and name it.
3. Click on next to enter the device properties.
4. Select the appropriate properties according to the hardware to be used.
5. Click on the next button to enter the new source.
6. Here select the Verilog MODULE and give the file name.
7. Click on next button and enter the entity name.
8. Select the define module.
9. Select the ports as input and output and name them.
10. Click on next and then to on finish.
11. Write the code for the project under the library entity.
12. Save the program.
13. Select the behavioral simulation option from the three modeling options.
14. Now select the syntax check.
15. If the syntax check comes out to be correct, then precede further, otherwise check
16. Now select simulation option and select the test bench option.
17. Initialize the clock and other properties from the window that appears on the
18. Give the clock pulse to one of the inputs and save the program.
19. Click on simulate to get the output.
Gate level Description
module mux4_1(D0,D1,D2,D3,S1,S0,Y);
input D0,D1,D2,D3,S1,S0;
output Y;
wire S1bar,S0bar,Y0,Y1,Y2,Y3;
not n1(S1bar,S1);
not n2(S0bar,S0);
and a1(Y0,S1bar,S0bar,D0);
and a2(Y1,S1bar,S0,D1);
and a3(Y2,S1,S0bar,D2);
and a4(Y3,S1,S0,D3);
or o1(Y,Y0,Y1,Y2,Y3);
Using Case statement
module mux_using_case(din_0 ,din_1,sel,mux_out);
input din_0, din_1, sel ;
output mux_out;
reg mux_out;
always @ (sel or din_0 or din_1)
begin : MUX
case(sel ) 1'b0 :
mux_out = din_0; 1'b1 :
mux_out = din_1;
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